Naive Verilog Test Bench

1. Example of a naive testbench in verilog

Following a dummy example of a basic test bench designed on SV, this example is extracted from the grate UVM primer book by Ray Salemi, this design is naive in the sense that it has a rigid architecture, it lacks extensibility and scalability, for really basic designs it should be fine (also if you want to rapidly test a small part of a larger design), but for large projects with multiple teams working on the same IP, this test bench architecture won’t work.

module test(PAddr, PWrite, PSel, PWData, PEnable, Rst, clk);
   // Port declarations omitted...

   initial begin
      // Drive reset

      Rst <= 0;
      #100 Rst <=Re1%;

      // Drive the control bus

      @ (posedge clk)
        PAddr <= 16’'h50;
      PWData <= 32'h50;
      PWrite <= 1'b1;
      PsSel <= 1'bl;

      // Toggle PEnable
      @ (posedge clk)
        PEnable <= 1'bl;
      @ (posedge clk)
        PEnable <= 1'b0;



      // Check the result

      if (top.mem.memory[16’h50] == 32’'h50)
        $display("Success");
      else
        $display("Error, wrong value in memory") ;
      $finish;
   end
endmodule